1. Field of the Invention
The present invention relates to carrier substrates for use in chip-scale packages and to chip-scale packages including such carrier substrates. Particularly, the present invention relates to carrier substrates fabricated from polymeric materials. Methods of fabricating chip-scale packages are also within the scope of the present invention.
2. Background of Related Art
In conventional semiconductor device fabrication processes, a number of distinct semiconductor devices, such as memory chips or microprocessors, are fabricated on a semiconductor substrate, such as a silicon wafer. After the desired structures, circuitry, and other features of each of the semiconductor devices have been fabricated upon the semiconductor substrate, the substrate is typically singulated to separate the individual semiconductor devices from one another.
Various post-fabrication processes, such as testing the circuits of each of the semiconductor devices and burn-in processes, may be employed either prior to or following singulation of the semiconductor substrate. These post-fabrication processes may be employed to impart the semiconductor devices with their intended functionality and to determine whether or not each of the individual semiconductor devices meets quality control specifications.
The individual semiconductor devices may then be packaged. Along with the trend in the semiconductor industry to decrease semiconductor device size and increase the density of structures of semiconductor devices, package sizes are also ever-decreasing. One type of semiconductor device package, the so-called xe2x80x9cchip-scale packagexe2x80x9d or xe2x80x9cchip-sized packagexe2x80x9d (xe2x80x9cCSPxe2x80x9d), consumes about the same amount of real estate upon a substrate as the bare semiconductor device itself. Such chip-scale packages typically include a carrier substrate having roughly the same surface area as the semiconductor device.
Some chip-scale packages include a semiconductor device and a polymeric carrier substrate. Exemplary chip-scale packages with polymeric carrier substrates are disclosed in U.S. Pat. No. 5,677,576 (hereinafter xe2x80x9cthe ""576 Patentxe2x80x9d), which issued to Masatoshi Akagawa on Oct. 14, 1997, U.S. Pat. No. 5,683,942 (hereinafter xe2x80x9cthe ""942 Patentxe2x80x9d), which issued to Keiichiro Kata et al. on Nov. 4, 1997, and U.S. Pat. No. 5,844,304 (hereinafter xe2x80x9cthe ""304 Patentxe2x80x9d), which issued to Keiichiro Kata et al. on Dec. 1, 1998.
The ""576 Patent discloses a chip-scale package that includes a semiconductor device, a layer of insulative material, through which bond pads of the semiconductor device are exposed, disposed on an active surface of the semiconductor device, and a conductive elastomer disposed adjacent the layer of insulative material and the bond pads of the semiconductor device. Conductive elements are positioned adjacent the conductive elastomer so as to facilitate the disposition of a conductive bump that is laterally offset from the bond pad location. A photoresist, including apertures through which portions of the conductive elements are exposed, is then disposed over the conductive elements and the conductive elastomer. Conductive bumps are disposed within the apertures and in communication with the conductive elements. The carrier substrate and method of the ""576 Patent are somewhat undesirable because the disposal of an additional layer of insulative material on the active surface of the semiconductor device may increase fabrication time and costs, as well as the likelihood of device failure. Moreover, as each of the bond pads is associated with a laterally extending conductive element, each of the conductive bumps is, somewhat undesirably, laterally offset from the location of its corresponding bond pad.
The ""942 Patent describes a carrier substrate including a polymer layer including conductive traces with raised contact pads disposed on a first side thereof and corresponding conductive bumps disposed on the other side thereof. The conductive traces and their corresponding conductive bumps communicate by means of electrically conductive vias through the carrier substrate. A layer of insulative material is disposed upon the active surface of the semiconductor device with which the carrier substrate is to be assembled, laterally adjacent the bond pads. The carrier substrate, which is pre-fabricated, is disposed adjacent the active surface of a semiconductor device by aligning the contact pads of the carrier substrate with the bond pads of the semiconductor device, disposing a quantity of adhesive material between the active surface and the carrier substrate, and applying pressure to the carrier substrate to abut the contact pads against their corresponding bond pads. Pressure is applied locally to the contact pads and, thus, to the bond pads through apertures defined through the carrier substrate. The carrier substrate of the ""942 Patent is somewhat undesirable in several respects. The disposal of a layer of insulative material laterally adjacent the bond pads of the semiconductor device increases fabrication time and costs, as well as the likelihood of device failure. The semiconductor device may be damaged while localized pressure is applied to the bond pads thereof, again undesirably increasing the likelihood of device failure and, therefore, fabrication costs. Moreover, since the carrier substrate of the ""942 Patent is pre-fabricated, it is possible that the raised contact pads of the carrier substrate may not properly align with their corresponding bond pads of the semiconductor device.
The polymeric carrier substrate of the ""304 Patent is fabricated directly upon an active surface of a semiconductor device. That carrier substrate, however, does not include electrically conductive vias that extend substantially longitudinally therethrough. Rather, a layer of insulative material is disposed on an active surface of a semiconductor device upon which the carrier substrate is to be fabricated, adjacent the bond pads thereof. Laterally extending conductive lines are fabricated on the layer of insulative material and in contact with corresponding bond pads of the semiconductor device. Conductive bumps are then disposed adjacent corresponding conductive lines and a layer of polymeric material applied to the semiconductor device so as to insulate the conductive lines. The conductive bumps are exposed through the layer of polymeric material. Since each of the conductive lines of the carrier substrate of the ""304 Patent extends substantially laterally from its corresponding bond pad, each of the conductive bumps is, somewhat undesirably, laterally offset from the location of its corresponding bond pad. Moreover, the disposal of an additional layer of insulative material on the active surface of the semiconductor device, through which the bond pads are disposed, increases fabrication time and costs, as well as the likelihood of device failure.
As the carrier substrate of such chip-scale packages is small, electrical connections between the semiconductor device and the carrier substrate are often made by flip-chip-type bonds or tape-automated bonding (xe2x80x9cTABxe2x80x9d). Due to the typical use of a carrier substrate that has a different coefficient of thermal expansion than the semiconductor substrate of the semiconductor device, these types of bonds may fail during operation of the semiconductor device.
Following packaging, the packaged semiconductor devices may be re-tested or otherwise processed to ensure that no damage occurred during packaging. The testing of individual packaged semiconductor devices is, however, somewhat undesirable since each package must be individually aligned with such testing or probing equipment.
Accordingly, there is a need for a chip-scale package with at least some conductive bumps or contacts that are not laterally offset from the position of their corresponding bond pad and for a packaging method that does not require the disposal of an additional layer of insulative material adjacent the active surface of the semiconductor device. There is also a need for a semiconductor packaging process that facilitates testing, probing, and bum-in of semiconductor devices without requiring the alignment of individual semiconductor devices and by which a plurality of reliable chip-scale packages may be substantially simultaneously assembled. An efficient chip-scale packaging process with a reduced incidence of semiconductor device failure is also needed. There is a further need for chip-scale packaged semiconductor devices that consume about the same amount of real estate as the semiconductor devices thereof and that withstand repeated exposure to the operating conditions of the semiconductor device.
The present invention includes a chip-scale package (xe2x80x9cCSPxe2x80x9d) including a semiconductor device having at least one bond pad on an active surface thereof and a carrier substrate, which is also referred to herein as a carrier, adjacent the active surface of the semiconductor device and including at least one electrically conductive via therethrough. The at least one electrically conductive via preferably extends directly through or substantially longitudinally through the carrier substrate and is alignable with the at least one bond pad of the semiconductor device. The carrier substrate may also include at least one conductive bump in communication with the at least one electrically conductive via and disposed opposite the semiconductor device. The at least one electrically conductive bump may be disposed adjacent the at least one electrically conductive via. Alternatively, the carrier substrate may carry at least one conductive trace that extends substantially laterally from the at least one electrically conductive via. The at least one conductive bump may be disposed in contact with the at least one electrically conductive trace and, therefore, the at least one electrically conductive bump may be laterally offset from its corresponding bond pad of the semiconductor device.
Preferably, the carrier substrate comprises a layer of polymeric material, such as a polyimide. The polymeric material is preferably disposed in a thickness or has a coefficient of thermal expansion that will not induce stress in the conductive links between the semiconductor device and the carrier substrate under the operating conditions of the semiconductor device (e.g., the operating temperature of the semiconductor device). Accordingly, in accordance with the method of the present invention, the carrier substrate may be secured to the active surface of the semiconductor device by disposing and spreading a quantity of polymeric material on the active surface of the semiconductor device to a substantially consistent thickness. Alternatively, a preformed film of the polymeric material may be adhered or otherwise secured to the active surface of the semiconductor device. The layer of polymeric material may be disposed on the semiconductor device either before or after the semiconductor device has been singulated from a wafer.
Apertures may be defined through the layer of polymeric material by known processes, such as by laser-drilling, by masking and etching, or by photoimaging the layer of polymeric material. These apertures may be defined after the layer of polymeric material has been secured to the active surface of the semiconductor device. Alternatively, if a preformed film of polymeric material is secured to the active surface of the semiconductor device, the apertures may also be preformed. If the layer of polymeric material comprises a preformed film of polymeric material having preformed apertures therethrough, each aperture is preferably substantially alignable with its corresponding bond pad of the semiconductor device as the polymeric film is secured to the active surface of the semiconductor device.
A quantity of conductive material may be disposed in each aperture of the layer of polymeric material and, therefore, in contact with the bond pad that corresponds to the aperture. Each aperture and the quantity of conductive material therein collectively define a conductive via of the carrier substrate.
Conductive traces that extend substantially laterally from selected ones of the electrically conductive vias may also be fabricated on the carrier substrate, opposite the semiconductor device. Preferably, these conductive traces are positioned to laterally offset the locations of contacts or conductive bumps of the carrier substrate relative to the locations of their corresponding bond pads of the semiconductor device. Accordingly, the conductive traces may impart the carrier substrate with a footprint that differs from that of the semiconductor device to which the carrier substrate is secured.
Conductive bumps may be disposed on a surface of the carrier substrate opposite the semiconductor device. Each conductive bump preferably communicates with at least one corresponding bond pad of the semiconductor device. Accordingly, the conductive bumps may be disposed in contact with either an electrically conductive via or a substantially laterally extending conductive trace of the carrier substrate.
Other features and advantages of the present invention will become apparent to those of ordinary skill in the art through a consideration of the ensuing description, the accompanying drawings, and the appended claims.